1. Field of the Invention
In one embodiment, the invention relates to a phase shift apparatus, and more particularly, to a clock generation circuit configured to generate a plurality of data signals having an adjustable phase relationship. In another embodiment, the phase shift apparatus may be a data interface circuit configured to receive a plurality of data signals from a data bus, and adjust a phase relationship between a clock signal and the plurality of data signals. In either embodiment, the plurality of data signals may be shifted by a first phase shift amount prior to being shifted by a second phase shift amount, such that the shifted data signals may be received by one or more system components at substantially the same time. As such, the phase shift apparatus may be included within any synchronous system or device, such as within a computer system, a data processing system, or a communications system or network.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many electronic systems include one or more synchronous components that rely on receiving related signals at substantially the same time to maintain proper operating characteristics of the electronic system. Such a synchronous system may be, in one example, a computer system, which typically includes a multitude of interrelated system components each designed to perform a particular operation in response to a clock signal. In some cases, the transfer of data between system components may be synchronized by one or more clock signals originating from a common source. In such a case, the system components may receive the one or more clock signals through a clocking network, which generally includes clock generation and distribution circuits.
In some cases, clock generation is accomplished by manipulating the output of a source, such as a crystal oscillator, to generate a plurality of clock signals according to the needs of various components within the computer system. The generated clock signals may then be fanned out to the system components, via a clock distribution network. In an ideal situation, the generated clock signals may be received simultaneously by each of the system components. In practice, however, timing delays and uncertainties of clock signal generation and distribution may cause the system components to receive clock signals at slightly different instances. In some cases, any variation in the arrival of a clock signal transition relative to a data signal transition may significantly impact system performance and/or reliability.
Such timing delays and uncertainties may include, for example, skewing of the clock signal transition relative to the data signal transitions received by the system components. In general, “skew” may be described herein as a variation in the arrival times between two related signals specified to occur at the same time. In some cases, clock skew may be introduced into the clocking network through load mismatches, routing parasitics (i.e., interlayer dielectric thickness, interconnect thickness and channel length mismatches), and/or variations in temperature, voltage, and process (i.e., trace conductor length, width, and composition mismatches, capacitive loading, etc.).
In some cases, clock skew may affect the timing margins of components within a synchronous system, such as a computer system. In most cases, for example, it is beneficial to properly align the clock and data signals received by the system components to ensure that a transition of the data signal occurs at the proper moment between the edges or active transitions of a clock signal. Synchronous systems, therefore, generally rely on data transitioning and remaining stable from a time at least a “setup time” before a clock transition until at least a “hold time” after the clock transition. Most synchronous system components have stringent setup and hold timing requirements, which are typically specified by a manufacturer of the system component.
As operating speeds increase, however, the setup and hold timing margins between active transitions of the clock and data signals are reduced, thereby decreasing the window within which a data transition can be successfully latched by a clock transition. For example, edge-sensitive flip-flops may be used to sample the data signals received by each of the system components. In such an example, a flip-flop may successfully latch a data signal if the data signal is stable during the critical setup and hold periods on either side of the clock transition. In some cases, however, clock skew may shift the clock transition sufficiently in time to cause a bit error to occur when the data is sampled. A “bit error”, as described herein, is a sampling error that occurs when a clock transition incorrectly samples a data signal.
In addition, clock skew may reduce the cycle time in which information can be passed between synchronous elements within a system component, e.g., between pipelined stages within a microprocessor. As operating speeds increase, clock skew may become an increasingly large portion of the total cycle time. When cycle times were 50 ns, for example, clock skew could occupy as much as 20% of the cycle time without degrading system performance. In high-speed systems having cycle times approaching 15 ns or less, however, only 10% of the timing budget may be allocated to clock skew. If clock skew exceeds such an allocated amount, the system will most likely perform unreliably.
In another example, a synchronous system may be any system within which data is transferred from one synchronous device (e.g., a transmitter) to another synchronous device (e.g., a receiver) in response to a clock transition. In general, data signals may be transferred from transmitter to receiver across one or more transmission lines in either a serial or parallel data format. Such a synchronous system may include, for example, data transmission between system components, or alternatively, data transmission within a communications system or network.
In some cases, data transmission within a synchronous system may be conducted over parallel transmission lines, sometimes referred to as a parallel data bus. In addition to clock skew, random noise induced within the parallel data bus may adversely effect data transmission. For example, bit errors may result if a sufficient amount of noise is induced within the parallel data bus when a receiver of the synchronous system samples the data signal. In general, noise may create data skew and/or jitter within one or more paths of the parallel data bus.
Data skew is often defined by variations between one data path and another. Although individual paths of a parallel data bus are generally routed within close proximity to each other, they are often not identical. As such, mismatches may exist between the individual data paths, thereby causing one or more data transitions to be “skewed” relative to the others. In other words, mismatches between individual data paths may cause the data transitions to arrive at slightly different times. Unfortunately, the amount and direction by which a data transition is skewed (i.e., temporally shifted by a positive or negative amount) depends on more than one factor and is often extremely hard, if not impossible, to predict. For example, the amount of data skew may depend on the physical differences between the parallel data paths, such as trace length, width, and composition mismatches, capacitive loading, etc. In addition, the amount of data skew may depend on the operating speed of the system, and in some cases, may increase as operating speeds increase.
Jitter, on the other hand, applies only to an individual path of the parallel data bus and generally results from time-varying components of noise sources. Jitter is often defined as the cycle-to-cycle variation in the “threshold crossings” of the data. In other words, jitter results in data samples taken near, but not exactly at, the desired sample locations of an individual data signal, such that a sample is temporally displaced by an unknown, though usually small interval (e.g., an interval substantially less than or equal to one clock cycle). As such, the overall effect of jitter is to shift a data signal sufficiently in time to cause incorrect sampling of the data signal by the clock signal, and thus, produce a bit error.
As such, numerous techniques have been used in an effort to minimize the effects of timing delays, e.g., clock skew, data skew, and jitter, which often lead to degradation in performance and reliability of a synchronous system. Most techniques, however, cannot in all conditions ensure that a data signal transition will occur at the critical moment between clock signal edges. In a semiconductor device, for example, one or more transmission lines may be routed having excess line lengths in an attempt to compensate for skew introduced by board trace length mismatches (i.e., mismatches in transmission line lengths between transmitting and receiving portions of a synchronous system). Such a technique, however, may disadvantageously increase the amount of noise introduced into the system (e.g., due to increased electromagnetic interference resulting from the increased line length). In addition, such a technique may introduce an amount of delay that is undesirably fixed by the circuit design and cannot be changed by a user of the system.
In another example, a variable number of active delay elements, such as buffers or inverters, may be included within individual transmission lines to impart a different amount of delay to each line. The amount of delay included within each line, however, may be undesirably fixed by the circuit design and cannot be changed by a user of the system. Therefore, each of the techniques described above suffer from the inability to control timing delays after board manufacture. In particular, the above techniques suffer from the inability to control timing delays due to temperature, voltage, and process, and thus, often lead to poor accuracy. In addition, the above techniques often increase the financial cost, power, and area consumed by the synchronous system.
In an alternative example, a phase-locked loop (PLL) or delay-locked loop (DLL) device may be used to generate and select a phase for shifting a clock signal transition relative to the data signal transitions received by the synchronous system. In general, a PLL is a closed-loop device that uses a voltage-controlled oscillator (VCO) to obtain accurate phase and frequency alignment between feedback and reference signals. A DLL device, on the other hand, generally differs from a PLL device in that it uses a delay line instead of a VCO to obtain accurate phase and frequency alignment between feedback and reference signals. As such, a PLL or DLL may beneficially provide a slightly variable, though highly consistent, amount of phase delay by which to shift the clock signal transition.
In general, a PLL or DLL may provide an incremental amount of delay, or phase resolution, which is inversely proportional to the number of stages, N, included within the oscillator or delay line. Unfortunately, the number of stages allowed within the oscillator or delay line is often limited by the maximum operating frequency, FMAX, of the PLL or DLL. In this manner, a PLL or DLL may provide a phase resolution of approximately 1/(2*FMAX*N), or the minimum delay of one stage, which in current technology may be about 50 picoseconds to about 150 picoseconds. As stated above, however, the window within which a data transition can be successfully latched by a clock transition decreases as operating speeds of synchronous systems increase. Therefore, a PLL or DLL device may not provide sufficient phase resolution for accurately controlling the timing delays between related signals within high-speed synchronous systems.
Therefore, it would be beneficial to provide an improved phase shift apparatus, which would preferably reduce the effects of clock skew, data skew and jitter within and/or between synchronous systems. In addition, the improved phase shift apparatus would provide a programmable means for controlling timing delays after manufacturing of the synchronous system. Furthermore, the improved phase shift apparatus would exhibit significantly increased accuracy and phase resolution over conventional solutions. Moreover, the improved phase shift apparatus would consume substantially less power and area, and cost less than conventional solutions.